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Micrel, Inc.
Pin Description: Signal Descriptions by Group (Continued)
KSZ9692PB, KSZ9692PB-S
Pin Number
T17, V18,
Pin Name
DADDR[13..0]
Pin Type
O
Pin Description
DDR Address Bus.
U17, T16,
W20, W19,
Y20, Y19,
W18, V17,
U16, T15,
Y18, V16
V13, U11,
DDATA[31..0]
I/O
DDR Data Bus.
V12, W13,
Y13, W12,
V11, U10,
V10, Y11,
W10, U9,
Y10, V9, W9,
Y9, W8, Y8,
Y7, W7, V7,
Y6, W6, V6,
Y5, V5, W5,
U5, T5, Y4,
V4, W4
T13, V14
U14
BA[1:0]
CSN
O
O
DDR Bank Address.
DDR Chip Select, asserted Low.
Chip select pins for DDR, the KSZ9692PB, KSZ9692PB-S supports only one
DDR bank.
T14
RASN
O
DDR Row Address Strobe, asserted Low.
The Row Address Strobe pin for DDR.
U15
CASN
O
DDR Column Address Strobe, asserted Low.
The Column Address Strobe pin for DDR.
V15
WEN
O
DDR Write Enable, asserted Low.
The write enable signal for DDR.
U8, T6
T12,Y12
DM[3:0]
O
Data Input/Output mask signals for DDR. DM is sampled High and is an output
mask signal for write accesses and an output enable signal for read accesses.
Input data is masked during a Write cycle. DM0 corresponds to DDATA[7:0],
DM1 corresponds to DDATA[15:8], DM2 corresponds to DDATA[23:16] and
DM3 corresponds to DDATA[31:24].
V8, U6
U12,W11
DQS[3:0]
I/O
DDR only Data Strobe
Input with read data, output with write data. DQS0 corresponds to DDATA[7:0],
DQS1 corresponds to DDATA[15:8].
May 2011
13
M9999-051111-4.0
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